Interface apparatus for integrated circuit testing

ABSTRACT

An apparatus and method for coupling a test head and probe card in an IC testing system incorporating patterned divider elements disposed between rows of signal conductors to provide matching characteristic impedance values along each row of signal conductors. The divider elements have a conductive layer formed thereon that is electrically connected to ground. Openings of various shapes and sized are formed in the conductive layer to adjust the characteristic impedance of a corresponding signal conductor. A method for determining the patterning required for characteristic impedance matching is also provided. Test dividers are provided with openings of different size, and characteristic impedance measurements are taken with the various openings aligned to a signal conductor. The size opening is then interpolated to provide a particular characteristic impedance value. By sizing the openings corresponding to each signal conductor for the same characteristic impedance value, characteristic impedance matching is provided.

FIELD OF THE INVENTION

[0001] The present invention relates to integrated circuit (IC) testing systems, and more particularly, to devices for coupling a test head with a probe card or dut board in an IC testing system.

DESCRIPTION OF THE RELATED ART

[0002] Wafer testing systems typically include a test head and a probe card. Packaged part testing systems typically include a test head and a dut board. The probe card or dut board includes a pattern of contacts for electrically probing or connecting to portions of an integrated circuit. The test head is configured to drive various contacts of the probe card or dut board to carry out particular test procedures within the integrated circuit. In the course of a test procedure, the test head receives output signals from the integrated circuit via the contacts of the probe card or dut board. The output signals are indicative of electrical characteristics of the integrated circuit under test. The probe card or dut board and the test head are uniquely configured for a particular integrated circuit and, in some cases, a particular test procedure. Accordingly, the probe card or dut board and/or the test head must be changed for different integrated circuits and test procedures.

[0003] The test head is electrically coupled to the probe card or dut board with a coupling apparatus (i.e., interface apparatus) often referred to as a “pogo” unit. The pogo unit engages the test head, or some intermediate coupling structure associated with the test head, and the probe card or dut board. The pogo unit includes an array of spring-loaded contacts referred to as pogo pins. The pogo pins act as signal and ground conductors, and are arranged to electrically couple contacts on the probe card or dut board to corresponding contacts on the test head. The spring force of the pogo pins helps to maintain uniformity of electrical contact between the various contacts of the probe card or dut board and the test head. When the test head and probe card or dut board are engaged with the pogo unit exerting pressure against the pogo pins, the pogo pins respond with a spring force that enhances coupling pressure. The resilience of the pins generally ensures adequate coupling pressure despite planar deformation of the test head or the probe card or dut board during a test procedure.

[0004] In many applications, the conductors are required to carry signals having very high frequency components, from 100's of MHz to 10 GHz in the near future and to 10's of GHz in the more distant future. Accordingly, the transmission line characteristics of the interface are of utmost importance. In particular the characteristic impedance, Z, of the signal path between the probe card or dut board and the test head is of prime interest. For optimal signal transfer between the test electronics and the device being tested, the characteristic impedance of all elements in the signal path should be closely matched. Accordingly, in many applications, it is desired that all critical signal paths have the same Z, for example 28, 50, or 75 Ohms. In other applications, it may be required that several different values of characteristic impedance be provided in the same interface.

SUMMARY OF THE INVENTION

[0005] An interface apparatus is used for integrated circuit testing. The apparatus includes a first plate having first locations, a second plate having second locations, conductors extending between the first locations on the first plate and the second locations on the second plate, and a conductive divider element spanning across ones of the conductors. The conductive divider element has a pattern of conductive material formed thereon.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a perspective diagram of a section of an interface apparatus for an IC testing tool according to one embodiment of the present invention;

[0007]FIG. 2 is sectional view of an interface apparatus according to one embodiment of the present invention taken generally normal to the conductors, or pogo pins;

[0008]FIG. 3a is a diagram of a conductor cell with grounded divider elements for characteristic impedance analysis according to one embodiment of the invention;

[0009]FIG. 3b is a diagram of a coaxial transmission line cell, which is a known impedance cell for analysis by comparison;

[0010]FIG. 3c is a diagram of a five wire line cell, which is a known impedance cell for analysis by comparison;

[0011]FIG. 4 is a diagram of a conductor cell with an opening or gap in the grounded divider elements according to one embodiment of the present invention;

[0012]FIG. 5a is a sectional diagram taken generally parallel to a row of conductors and showing an elevation of the row of conductors and a divider element with a patterned conductive layer according to one embodiment of the present invention;

[0013]FIG. 5b is a sectional diagram taken generally parallel to a row of conductors and showing an elevation of the row of conductors and a divider element with a patterned conductive layer according to one embodiment of the present invention;

[0014]FIG. 6 is a sectional plan view of a row of conductors situated between two divider elements comprising a grounded conductive layer according to an exemplary application of the present invention;

[0015]FIG. 7 is an elevation view of a test divider having a patterned conductive layer with vertical strips of varied thickness removed for experimentally tuning characteristic impedance of a given cell;

[0016]FIG. 8 is an elevation view of a test divider having a patterned conductive layer with horizontally tapered polygons removed for experimentally tuning characteristic impedance of a given cell;

[0017]FIG. 9 is a curve showing characteristic impedance of an exemplary cell as a function of the width of an opening in the conductive layer;

[0018]FIG. 10 is a curve showing characteristic impedance of an exemplary cell as a function of the percentage of the conductor layer remaining on the divider element in the cell;

[0019]FIG. 11 is a plan view of a vertically patterned divider element for an exemplary cell;

[0020]FIG. 12 is a plan view of a horizontally patterned divider element for an exemplary cell;

[0021]FIG. 13 is a sectional view of a row of conductors in which characteristic impedance of the conductors is tuned by altering the size of the conductors; and

[0022]FIG. 14 is a sectional view of a row of conductors in which characteristic impedance of the conductors is tuned by altering the spacing of the conductors.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention is directed to a device for coupling a test head with a probe card or dut board in an IC testing system using multiple signal conductors and ground conductors that provides improved characteristic impedance matching between the signal conductors. In one embodiment, the present invention is an improvement upon the invention of commonly assigned and pending U.S. patent application Ser. No. 09/126,267 which is incorporated herein by reference. Divider elements having a conductive layer thereon and disposed between rows of signal conductors, as taught in Ser. No. 09/126,267, are modified to provide matching characteristic impedance values for the signal conductors within a row. The characteristic impedance of the conductors in a row can have undesirable conductor-to-conductor variation in a testing interface. For example, the distance from the center of the signal conductors to the divider elements may vary along the row of signal conductors when each row of signal conductors is disposed along a different radius centered beyond the interface apparatus. In one embodiment of the present invention openings of various shapes and sizes are formed in the conductive layer of the divider elements to correspond to the location of the signal conductors, adjusting the characteristic impedance. By sizing the openings corresponding to each signal conductor along a row of signal conductors to provide the same characteristic impedance, characteristic impedance matching is achieved.

[0024] Another embodiment of the present invention is directed to test divider devices and a method for using the test dividers to experimentally determine the sizes for openings that will provide characteristic impedance matching. Test dividers are provided that are fabricated from the same material as the divider sections with the same conductive layer thereon. Openings of the desired shape are formed in the conductive layer at various sizes. A pair of mirror-image test dividers is then inserted on either side of a row of signal conductors with openings aligned to a particular signal conductor and characteristic impedance measurements are taken. The procedure is repeated for each of the variously sized openings, then the entire procedure is repeated for another specific signal conductor. The opening size is interpolated for each signal conductor that will provide the desired characteristic impedance. Openings are then formed in a divider element having the sizes determined for the corresponding signal conductors.

[0025]FIG. 1 shows a section of an interface apparatus 12 for coupling a test head and a probe card during testing of an integrated circuit on a semiconductor wafer. It should be understood that the invention is not limited to a wafer testing apparatus, but can also be practiced in a packaged part testing embodiment. Interface apparatus 12 can be directly coupled between the test head and probe card. Alternatively, the test head and/or probe card may be equipped with intermediate coupling structures that interface with interface apparatus 12. As shown in FIG. 1, interface apparatus 12 includes a first plate 18, a second plate 20, conduits 22, and dividing elements 24. First plate 18 is disposed adjacent the test head (not shown), whereas second plate 20 is disposed adjacent the probe card (not shown). Conduits 22 and dividing elements 24 extend between first and second plates 18,20. Conduits 22 are generally elongated and tubular and may be, for example, circular or rectangular in cross-section. Each conduit 22 contains a spring-loaded conducting element (not shown), such as the type commonly referred to as a pogo pin. As an alternative, conduits 22 could accommodate a pin-and-socket connector as the conducting element. The conducting element electrically couples a contact associated with the test head to a corresponding contact associated with the probe card. The contacts associated with the test head and probe card may comprise pins.

[0026] First plate 18 includes first grooves 26, to receive the top edges of divider elements 24, and first sockets 28, to receive the top of conduits 22. Similarly, second plate 20 includes second grooves 30 and second sockets 32. First and second plates 18,20 are preferably annular forming a section of a ring-like structure, as shown in FIG. 1. However other configurations are possible. Sockets 28,32 are arranged in radial rows and grooves 26,30 are oriented along radii between the rows of sockets. Conducting elements (conductors) 23 and divider elements 24 are similarly arranged in a radial pattern as shown in FIG. 2 with the center of the radii beyond the boundary of the interface apparatus. As is shown in FIG. 2, the distance from the center of the conductors to the adjacent divider elements is greater proceeding further along the radius (to the left in FIG. 2).

[0027] The conductors 23 carry signals and grounds from one plate to the other plate. The divider elements 24 disposed between rows of conductors may include one or more conductive layers to provide shielding for signal transmission in the conductors 23. The conductive layers of the divider elements 24 are typically connected to ground potential and serve to provide shielding between the signal conductors in one row on one side of the divider and the signal conductors in the row on the other side of the divider.

[0028] As previously discussed, the conductors 23 may be required to carry signals having very high frequency components, from 100's of MHz to 10 GHz and to 10's of GHz in the future. Accordingly, the transmission line characteristics of the interface are of utmost importance. In particular the characteristic impedance, Z, of the signal path between the plates is of prime interest. For optimal signal transfer between the test electronics and the device being tested, the characteristic impedance of all elements in the signal path should be closely matched. Accordingly, in many applications, it is desired that all critical signal paths have the same Z, for example 28, 50, or 75 Ohms. In other applications, it may be required that several different values of characteristic impedance be provided in the same interface.

[0029] The designer of an interface is typically not free to select the geometric arrangement of the conductors. In many cases a radial arrangement is necessary. The row-to-row spacing between the conductors increases with increasing distance from the center of the radius on which the conductors are positioned. Accordingly, with all other factors and dimensions held constant, the characteristic impedance will increase along a row of conductors with increasing distance from the center of the interface (located beyond the boundary of the interface apparatus). Thus it is important to have a means to design and construct an interface that provides controlled characteristic impedance for all critical signals of interest.

[0030] In an interface having a row of conductors where all signal conductors should have close to the same nominal characteristic impedance, it would be typical for the designer to set the physical parameters of a signal pin “cell” at the desired nominal characteristic impedance at a point midway between the two ends of the row and then estimate the characteristic impedance at each end. In certain cases the non-linearity in the variation of the characteristic impedance along the row may be significantly pronounced, and in such cases the designer can adjust the point at which the nominal characteristic impedance occurs in order to minimize the end-to-end variation. Also, the designer could specify varying conductor sizes along the row to further adjust individual characteristic impedance values and to minimize the overall variation.

[0031] Along an electrical signal transmission path structure that is uniformly constructed along its length, the characteristic impedance may be analyzed by considering the geometry of a cross section of the structure. The structure includes a forward conductive path from signal source to signal sink and a parallel return conductive path. In practice, the return path is typically tied to ground potential. The cross section is taken at right angles to the path, and the path is uniform so long as the cross section is the same at every point along the path. Provided that the materials involved are not ferimagnetic, the signal path is virtually lossless, and insulating materials involved have a uniform permittivityivity, which is the case in virtually all applications of interest, the characteristic impedance of the line is given by

Z=[{square root}ε _(R) ]/[v C] Ohms  (Eq. 1)

[0032] Where ε_(R)=the relative permittivity=1 in air or vacuum

[0033] v=speed of light=3×10⁸ meters/sec.

[0034] C=Capacitance of the line in farads/meter

[0035] The capacitance of the line is the capacitance between the two parallel conductors. Generally, capacitance between two conductive bodies is proportional to the relative permittivity ε_(R) of the material between the conductors. Generally, capacitance increases with increasing surface area of the conductors facing one another, and decreases with increasing distance between the conductors. In a cross sectional representation, surface areas of the conductors are proportional to their perimeters. In virtually all analysis, it is assumed that the conductivity of the conductors is infinite which is consistent with the virtually lossless assumption. The characteristic impedance can be adjusted or designed in by controlling the distance between conductors and by varying the exposed surface areas and shapes. That is, increasing the spacing will decrease Z, while decreasing the effective surface area will increase Z.

[0036] Numerous approaches have been followed over the years to determine Z of a uniform transmission line given its cross sectional structure. In general the procedure is to mathematically apply a potential difference across the two conductors and solve Laplace's equation, ∇²φ=0, to find the two dimensional electric field. From knowledge of the field, the charge on the conductors is determined, and then the capacitance may be found. The literature is rich in approaches to methods of solution. Solutions may be handled using a variety of methods, including:

[0037] 1. direct analysis for simple geometries,

[0038] 2. constructing physical models and performing actual physical measurements of the field as disclosed in Shadowitz, The Electromagnetic Field, p. 359-360, Dover Publications, Inc., 1988, incorporated herein by reference.

[0039] 3. graphical approximations as disclosed in Stewart, Circuit Analysis of Transmission Lines, p. 59-60, John Wiley & Sons, Inc., 1958, incorporated herein by reference,

[0040] 4. mathematical conformal transformation of the actual geometry to a geometry having a known solution, or

[0041] 5. numerical techniques, including iterative solutions to finite difference equations which approximate Laplace's equation.

[0042] Direct analysis techniques include superposition approaches where applicable and the use of image techniques for the substitution of a known geometry into the given geometry. In addition, various handbooks are available that provide formulae for various geometries of interest.

[0043] The application of formal techniques to even simple geometries, however, requires considerable specialized skills. In the practical world, where geometries can be complex, a combination of experience-based approximation and focused experimentation is typically required to engineer a solution. This process may be supported to varying degrees by computer modeling and simulation, for example by difference equation techniques, if desired. Herein, an experimental approach to the practice of the present invention is described.

[0044] In the apparatus shown in FIGS. 1 and 2, the characteristic impedance of a conductor 23 will be affected by the conductive divider elements 24 that are adjacent to it as well as the two conductors that are located on either side of it in its row. In a high performance interface apparatus, it is usually preferred to alternate signal and ground connections along a row of conductors. The conductors immediately adjacent to a given signal-carrying conductor are normally ground carrying conductors. That is, the signal conductor provides the signal path from source to sink, and the combination of the divider elements and the two adjacent ground conductors provide the return path.

[0045] Preferably, a single row will contain an odd number (2N+1) of conductors. Numbering the conductors from 1 to 2N+1 from one end of the row to the other, the odd-numbered conductors carry ground, and the even-numbered conductors carry signals. Thus, in typical application, a signal conductor is surrounded on four sides by ground conductors. The apparatus configuration shown in FIG. 3a, comprising a signal conductor 23 s, two ground conductors 23 g, and sections of two conductively coated divider elements 24, will be referred to as a “cell.” The signal conductor 23 s and ground conductors 23 g each have a diameter of d. The center-to-center spacing between the signal conductor and each adjacent ground conductor is S. The distance between the center of the signal conductor 23 s and each divider element 24 is W/2. A first order approximation to the characteristic impedance of this cell can be made be comparing it to similar transmission line configurations having known expressions for their characteristic impedance. The well-known handbook, Reference Data for Radio Engineers, fourth edition, International Telephone and Telegraph Corporation, eighth printing September 1962, incorporated herein by reference, provides approximate formulae for numerous transmission line configurations.

[0046] Two configurations, found in the handbook, that bear similarities to the present situation are illustrated in FIGS. 3b and 3 c. FIG. 3b illustrates is the familiar case of coaxial cylinders having characteristic impedance:

Z _(COAX)=(138/{square root}ε_(R))Log₁₀(D_(COAX) /d)  (Eq. 2)

[0047] where ε_(R) is the dielectric constant or relative permeability and is equal to 1.0 in air, D is the diameter of the coax ground 25 g, and d is the diameter of the signal conductor 23 s. FIG. 3c is referred to in the handbook as a “Five-wire Line,” having approximate characteristic impedance given by:

Z _(5 WIRE)=(173/{square root}ε_(R))Log₁₀(D_(5WIRE)/0.933d)   (Eq. 3)

Or,

Z _(5 WIRE)=(173/{square root}ε_(R))Log₁₀ ({square root}2h/0.933d)  (Eq. 4)

[0048] where h is the distance from a signal conductor 23 s to each of four surrounding ground conductors 23 g.

[0049] It is interesting that for similar dimensions (i.e., h=D/2 and D_(COAX)=D_(5WIRE)) that the coaxial cable and the five-wire line configuration provide similar results. For example, with representative dimensions corresponding to an interface of the type in question would be d=50 mils, and D_(COAX)=2h=200 mils. These values yield Z_(COAX)=83.0 ohms and Z_(5WIRE)=83.3 ohms with an air dielectric (ε_(R)=1). For cases where D_(COAX)=2 h, the two configurations give similar results within approximately +/−6.5% for values of 2 h/d between 3 and 6.5. This suggests that similar formulae can be adapted to different geometric arrangements.

[0050] Accordingly, either of the configurations in FIGS. 3B and 3C can be adapted to estimate an approximate value of the characteristic impedance of the configuration of interest in FIG. 3A. Herein, only the adaptation of FIG. 3B is discussed; a similar procedure may be followed with respect to FIG. 3C. To adapt FIG. 3B, D_(EQUIV), an equivalent effective average distance from the center of the signal conductor to the ground carrying components, is determined and used in place of D_(COAX). In practice the aspect ratio of a cell is not one as it is in FIGS. 3B and 3C. For example, the conductor-to-conductor spacing, S in FIG. 3A, may be a factor of two or more greater, than the distance from the center of the conductor to the conductive surface of the divider. However, from actual measurement data of cells having an approximate aspect ratio of two, a reasonable approximation is obtained by calculating:

D _(EQUIV)=(2S−0.9d+W)/2  (Eq 5)

[0051] Then the characteristic impedance of the cell is approximated by

Z _(CELL)≈138 {square root}ε_(R)Log₁₀(D_(EQUIV) /d)  (Eq 6)

[0052] Where: ε_(R) is the dielectric constant or relative permittivity (=1 in air), S is the center to center spacing of the conductors in the cell, d is the diameter of the conductors, and W is the distance from the conductive surface of one divider element to the conductive surface of the other divider element at the location of the signal conductor.

[0053] For example, the cell containing signal conductor 23S2 in FIG. 6 (to be considered in more detail later) has the following parameters: ε_(R)=1, S=0.100, d=0.065, and W=0.109. This yields Z_(CELL)=38.1 ohms, which compares favorably with the measured value of 39.4 ohms, the difference being less than 5%.

[0054] As can be seen in FIG. 2, the spacing between the divider elements, W, increases with increasing distance from the center of the radii on which the rows of conductors lie. If the outermost signal pin is X times further from the center than the innermost signal pin, then the value of W is X times greater at the outer circumference then at the inner circumference. Accordingly, with all other dimensions held constant, the characteristic impedance will increase along a row with increasing distance from the center of the interface. D_(EQUIV) may be rewritten as a function of the radial distance from the center as follows:

D _(EQUIV)=(2S−0.9d+(W _(i))*(R/R _(i)))/2  (Eq. 7)

[0055] Where:

[0056] R_(i)=distance from the center to the innermost signal conductor

[0057] W_(i)=distance between the divider elements at R_(i)

[0058] R=distance from the center to the conductor in question

[0059] In a high frequency test interface, all signal conductors in a row should have close to the same nominal characteristic impedance. It would be typical for the designer to set the physical parameters of a signal pin “cell” at the desired nominal characteristic impedance at a point midway between the two ends of the row and then estimate the characteristic impedance at each end. In certain cases the non-linearity in the variation of the characteristic impedances along the row may be significantly pronounced, and in such cases the designer can adjust the point at which the nominal characteristic impedance occurs in order to minimize the end-to-end variation.

Adjusting the Conductive Area of the Divider Elements

[0060] Referring again to FIG. 3a, the conductive layers on the divider elements 24 within the proximity of a signal conductor 23 s form a significant portion of the area of the effective capacitor between the signal conductor and ground potential. If the area is decreased, the capacitance is decreased, and the characteristic impedance will be increased. The conductive layers of the divider elements may be fashioned from circuit board stock having a conductive layer, typically copper, clad to an insulating substrate. The conductive area can be reduced by the process of etching away portions of the conductive layer according to a predetermined pattern. This may be achieved by the normal process of producing a patterned conductive layer on a printed circuit board. FIG. 4 shows a sectional view of a cell that has been tuned (i.e., the characteristic impedance has been adjusted) by removing a portion of the conductive layer on the divider element. A vertical (perpendicular to the page) strip of width g has been removed from the conductive layer 36 of both divider elements at the location of the signal conductor to form an opening 38. Although only one vertical strip per divider is indicated in FIG. 4, it is possible to remove a plurality of vertical strips within a cell if it is so desired.

[0061]FIG. 5A is a sectional view of an interface apparatus showing an elevation of a row of four cells 39 within the interface. It shows the five ground conductors 23 g and four signal conductors 23 s. A divider element 24 is shown behind the conductors 23. The divider element is coated with a conductive layer 36. A vertical strip of the conductive layer is removed at each signal conductor position forming vertical openings 38 v. It is seen that the vertical openings 38 v do not go all the way to the top and bottom of the divider element. This is to provide conductive material to connect all conductive regions of the divider element to provide ground continuity. Also, the conductive area along the top and bottom of the divider element makes contact with the ground connection provided in the top and/or bottom plates 18,20 of the interface by way of the grooves 26,30. It is seen in FIG. 5A that the vertical openings 38 v in the conductive layer 36 become increasingly wider in moving from the outermost cell 39 o to the innermost cell 39 i. This illustrates the concept where an increasing amount of material is removed with decreasing distance from the center of the radius on which the conductors are located. This has the desired effect of offsetting the effects that cause the characteristic impedance to decrease with decreasing distance to the center of the interface in order to maintain nearly constant characteristic impedance along the entire row of signal conductors.

[0062]FIG. 5B is also a sectional view of an interface apparatus showing an elevation of a row of four cells 39 within the interface comprising the five ground conductors 23 g and four signal conductors 23 s. A divider element 24 is shown behind the conductors 23 with conductive layer 36 on the divider element. A plurality of horizontal strips of the conductive layer 36 are removed through each cell 39 to form horizontal openings 38 h. It is observed that the width of the non-conductive strips becomes wider in moving from the outermost cell 39 o to the innermost cell 39 i. This again illustrates the concept where an increasing amount of material is removed with decreasing distance from the center of the radius on which the conductors are located. This again has the desired effect of offsetting the effects that cause the characteristic impedance to decrease with decreasing distance to the center of the interface in order to maintain nearly constant characteristic impedance along the entire row of signal conductors. The number of horizontal openings 38 h is somewhat arbitrary. The intent is to uniformly distribute the removed areas of the conductive layer along the path of the signal. However, it is desired to keep the width of each opening greater than approximately twice the distance from the signal conductor to the surface of the conductive layer in order to minimize the effects of fringing, which decrease the effective area of the removed conductive material.

[0063] Clearly, many alternative patterns are possible. Patterns where the conducting segments are all parallel with one another and to the conductors provide configurations where the transmission line is uniform along the signal conductor. Such patterns will be referred to as vertical patterns. and these may be analyzed in the traditional manner using a two dimensional cross section, such as in FIG. 4, which shows where strips of conductive material, parallel to the signal conductor, have been removed. The resulting reduction in conductive area is represented by the gaps in the conductive layers on the divider elements. Exact analysis of FIG. 4, even with just one gap per divider element, is very difficult because the ground conductor structure comprises several elements. With more gaps, the problem becomes even more difficult. Accordingly, experimental techniques such as those described later provide a practical means of solution.

[0064] In addition, horizontal patterns, as shown in FIG. 5B, are possible as well as cross-hatched or checkerboard patterns, which combine vertical and horizontal features. In these cases, the transmission line is no longer uniform; rather it is a series of discontinuous segments; the transition from segment to segment represents a potential change in characteristic impedance. These cases do not lend themselves to the usual two-dimensional analysis approaches, which all assume uniformity. However, numerical analysis approaches based on three-dimensional difference equations are possible. It is also observed that the typical length of a conductor is between approximately one inch and three inches and that the wavelength of a 1 GHz signal in air is approximately 12 inches. Accordingly, with the overall length of a conductor being typically less than 2 ½ to three inches, the distance between discontinuities is considerably less than one wavelength. However, at frequencies of 10 GHz or more, such discontinuities become increasingly undesirable, and vertical patterns would often be preferred. Also, as is well known, fringing of the electric field occurs near the boundary of a conductive area and a non-conductive area. On a microscopic basis, this has the effect of blurring the transition from one segment to the next. Accordingly, for a first approximation, it is reasonable to consider the effects of such patterning on a basis of the effect of overall reduction of area. This presumes that the patterning is such that the area reduction is uniformly distributed over the length of the conductor and is reasonably fine grained. However, the features of the pattern should be large enough so that they are not obliterated and rendered ineffective by fringing effects. (For example, removing conductive material at only one end of the path would not be consistent with these presumptions, nor would creating patterns with features on the order of a small fraction of the distance from the signal conductor to the conductive surface of the divider element.)

[0065] The amount by which the capacitance of a given cell is to be reduced to achieve a desired increase in characteristic impedance may be determined as follows:

[0066] 1. The characteristic impedance, Z_(OR), of the cell without any conductive material removed is first determined, either by estimate or by measurement.

[0067] 2. The effective total capacitance per unit length, C_(OR), of the cell without any conductive material removed can be calculated as C_(OR)={square root}ε_(R)/vZ_(OR).

[0068] 3. The effective total capacitance per unit length, C_(DES), of the cell having the desired characteristic impedance Z_(DES) can also be calculated as C_(DES)={square root}ε_(R)/ vZ_(OR).

[0069] 4. Consequently, the cell capacitance per unit length is to be reduced by an amount equal to C_(OR)−C_(DES)

[0070] (Note that it may be most convenient to work in units of femtofarads/millimeter (ff/mm). In this case the formulae above reduce to C=1000({square root}ε_(R))/0.3Z, where Z is in Ohms.)

Specific Case

[0071] An interface of the type illustrated in FIG. 1 is now considered as a specific case. FIG. 6 is a sectional plan view of the center row of conductors in an interface apparatus and its adjacent divider elements 24. The rows of conductors 23 are arranged radially (i.e., each is along a particular radius of a single circle), the angle between rows is approximately 1.53 degrees. The adjacent divider elements as shown do not have patterns etched in their conductive surfaces. The overall height of the structure in this case is approximately 2½ inches and the width of the upper plate is approximately 1 ¾ inches.

[0072] The distance from the center of the conductor row radii to the center of the innermost conductor of each row is 4.046 inches. The center-to-center spacing of conductors along a row is 0.100 inches; and, consequently, the distance from the radius on which the conductors lie to the center of the outermost signal conductor (23S1) is 4.746 inches. The divider elements 24 are arranged to lie on radii of that are midway between two rows of conductors. Accordingly, the angle formed between a row of conductors and an adjacent divider element is approximately 0.765 degrees. The overall thickness of a divider element is approximately 17 mils to 18 mils (thousandths of one inch). A divider element can be made of printed circuit board material having a substrate made of insulating material that is covered by a film of conducting material, such as copper, to form a conductive layer (36). In this case the thickness of the conductive layer is approximately 0.5 mils or less. With such a thin conductive layer, accuracy in etching patterns on the circuit board has been reported to be as good as 0.1 mils.

[0073] The diameter of the conductors 23 used in this particular interface example is 0.065 inches or 65 mils. The distance between the conductive layers 36 of the divider elements 24 at the center of the outmost signal conductor 23 s 1 is determined to be approximately 109 mils; and at the center of the innermost signal conductor 23 s 4, is approximately 93 mils.

[0074] In this particular interface, which is based upon an actual test system configuration, the pattern of signal conductors and ground conductors in each row is the same. In particular the innermost conductor in each row is a ground conductor 23 g 4, and the outermost conductor is a signal conductor. Along a row, ground conductors 23 g 1,23 g 2,23 g 3,23 g 4 and signal conductors 23 s 1,23 s 2,23 s 3,23 s 4 alternate as shown in FIG. 6. Accordingly, ground and signal conductors in adjacent rows are adjacent to one another. In other known systems, signal conductors and ground conductors in adjacent rows alternate in a checkerboard fashion such that neither two signal conductors nor two ground conductors are ever adjacent to one another to minimize cross talk.

[0075] To be more specific, a system having a checkerboard arrangement of signal and ground conductors is one where the four closest neighbors to a signal conductor is a ground conductor. For example, along one row, the conductors would be arranged in a sequence ground, signal, ground, signal, etc. and along the two adjacent rows, the conductors would be arranged in the sequence signal, ground, signal, ground, etc. Of course, at the boundaries, signal conductors might only have three neighbors. However, extra ground conductors can be placed at the ends of rows or beside rows to provide four grounded neighbors to every such signal conductor. The arrangement of the signal conductors is generally determined by the design of the test head. It has been found that with the checkerboard arrangement, dividing elements in an interface such as that shown in FIG. 1 are generally not needed between the rows to eliminate cross talk and signal-to-signal interference. Thus, with the checkerboard arrangement, the dividing elements are most useful to provide controlled characteristic impedance of the signal conductors by the approach described herein. Now, in a system where the pattern of signal conductors and ground conductors are the same along adjacent rows, the closest neighbors of a signal conductor may be two other signal conductors and two ground conductors. In such a non-checkerboard system, the dividing elements have an important role in minimizing the cross talk and signal-to-signal interference. In this case, removing conductive material from the divider to control the impedance can have the unwanted effect of reducing the effectiveness of the row-to-row shielding. The choice of pattern will effect the resulting shielding, and the degree of shielding loss vs. the control of characteristic impedance is a trade-off to be considered in non-checkerboard arrangements.

[0076] Signal conductors 23S2, 23S3, and 23S4 are in cell-like structures, as previously discussed. However, signal conductor 23S1, in the outermost position, is adjacent to only one ground conductor 23 g 1 and exposed to air on the side opposite to this ground conductor. Accordingly, the capacitance seen by signal conductor 23S1 is less than that seen by signal conductor 23S2 and we can expect that the characteristic impedance of signal conductor 23S1 is higher than that of signal conductor 23S2. Measurements made using Time Domain Reflectrometry (TDR) confirm this. In particular, with divider elements in place that are fully covered with conductive material, the characteristic impedance of signal conductor 23S1 measured approximately 50 ohms and the characteristic impedance of signal conductor 23S2 measured approximately 39.4 ohms. With the divider elements removed (and with the adjacent signal conductors disconnected) the measurements were approximately 69 ohms and 60 ohms respectively. In making these measurements and the measurements to be described later, it is important that all of the neighboring ground conductors are in fact connected to ground.

[0077] Because signal conductors 23S3 and 23S4 are in environments similar to that of signal conductor 23S2 but with successively closer spacing between signal conductor and divider element, it is to be expected that, with divider elements installed that are fully covered with a conductive layer, the characteristic impedances of signal conductors 23S3 and 23S4 will be successively lower than that of signal conductor 23S2. However, in the absence of conductive divider elements, the environments of 23S2 and 23S3 are more closely identical to that of signal conductor 23S2 and their characteristic impedances will be more closely matched.

[0078] Determining the characteristic impedance of a signal conductor with and without a divider element that is fully covered with a conductive layer indicates the range of characteristic impedances that can be derived by patterning the conductive layer on the divider element. In the case of signal conductor 23S1, the available range is approximately 50 to 69 ohms. In the case of signal conductor 23S2, the available range is approximately 39 to 60 ohms.

[0079]FIGS. 7 and 8 show views of test dividers 40,50 that can be used in conjunction with TDR measurements to characterize the characteristic impedance of a signal conductor as a function of the pattern on the test dividers. These test dividers are made from the same materials as the actual divider elements, and they are made in mirror image pairs so that they may be placed on opposite sides of a signal conductor. As shown, the patterns are constructed to test the effects of a pattern on a single signal conductor at a time; that is, the horizontal spacing in the patterns does not necessarily conform to the spacing of signal conductors along a row. In use, the test dividers are inserted into the slots 26 and 30 in the first and second plates 18,20 and positioned so that a desired opening or point in tapered openings is aligned with the signal conductor to be tested. The characteristic impedance of the signal conductor is then measured by using, for example, TDR. By measuring the characteristic impedance at a number of different divider positions, data can be gathered that will allow the actual patterns for a desired interface to be designed.

[0080] The patterns in the test divider 40 in FIG. 7 are targeted for designing patterned divider elements having single vertical openings at one or more signal conductors, similar to the divider element shown in FIG. 5a. Vertical openings 41-45 are formed in a conductive layer 36 on the test divider 40. The vertical openings 41-45 have progressively greater widths that can be selected in large graduated steps. The vertical openings 41-45 are sequentially aligned with a particular signal conductor, and the characteristic impedance is measured. The opening width can then be interpolated for a desired characteristic impedance. The patterns in the test divider 50 in FIG. 8 are targeted for designing patterned divider elements having horizontal spaces in the vicinity of one or more signal conductors, similar to the divider element shown in FIG. 5b. Tapered horizontal openings 51,52 are formed in a conductive layer 36 on the test divider 50. The tapered openings 51,52 are aligned to signal conductor being tested at points with progressively more or less of the conductive layer removed and characteristic impedance measurements are taken. The percentage of the conductive layer to be removed at each signal conductor location can then be interpolated from the characteristic impedance measurements. Other forms of test dividers can readily be developed to evaluate and characterize other styles of patterns.

[0081] To illustrate the use of the test dividers, a case is considered in which it is desired to design patterns for signal conductor 23S2 such that signal conductor 23S2 will have a characteristic impedance of 50 ohms. First, vertical patterns are designed. The pair of test dividers 40 of FIG. 7 is inserted into the interface and corresponding selected openings are aligned with signal conductor 23S2 such that, for example, a line between the centers of the corresponding openings on the two test dividers passes through the center of signal conductor 23S2. Offset alignments are possible, but in order to have minimal effect on adjacent cells in the row, especially in the case of wide spaces, the foregoing alignment is generally preferred. It should be noted that the resulting characteristic impedance will typically vary somewhat with the alignment, so care is suggested in performing this step. Once the test dividers are appropriately aligned, the characteristic impedance of signal conductor 23S2 is measured. Other opening pairs are aligned with signal conductor 23S2, and the characteristic impedance is measured in each case. In this particular example, the following results were measured using TDR. Width of Impedance Opening (mils) (Ohms)  31 40.4 110 51.6 150 55.4 180 56.8

[0082] These data points are plotted in FIG. 9. From this plot, it is found that the approximate width for achieving a characteristic impedance of 50 ohms is 98 mils.

[0083] Now horizontal patterns are designed. The pair of test dividers 50 of FIG. 8 is inserted into the interface. It is noted that the patterns vary continuously along the width of these test dividers. In practice, the test dividers are positioned and the characteristic impedance measured at three or four different points of insertion. At each point, care is taken to ensure that the two dividers are equally inserted so that the area of removed conductive layer exposed to the signal conductor is the same on both test dividers. Vertical lines 56-59 projected on the divider at a point corresponding to the centerline of the signal conductor 23S2 are useful in determining the fraction of conductor removed or remaining. In particular, the combined length of the line segment that coincides with the conductor divided by the total length of the line indicates the fractional area of remaining conductor. In this particular example, the following results were measured. Percentage of Remaining Impedance Conductor (Ohms) 34 52.9 56 49.3 82 46.0 100  39.4

[0084] Note that the case of 100% remaining conductor is the same as the case having a test divider entirely covered with a conductive layer as previously described. These data points are plotted in FIG. 10. From this plot, it is found that the approximate percentage of remaining conductive layer for achieving a characteristic impedance of 50 ohms is 51%.

[0085] To continue the example, vertical and horizontal patterns are now designed such that either will provide a characteristic impedance of 50 ohms for all signal conductors along a row in the interface. The procedure outlined above may be followed for signal conductors 23S3 and 23S4. It is noted that the W dimension for signal conductor 23S3 is approximately 95% of that for signal conductor 23S2, and the W dimension for signal conductor 23S4 is 95% of that for signal conductor 23S3. Consequently, the characteristic impedance for signal conductors 23S3 and 23S4 vary only slightly from each other and from that of signal conductor 23S2. It is also noted, that due to its different arrangement, signal conductor 23S1 has a substantially higher characteristic impedance than the other signal conductors in this example. In fact the characteristic impedance of signal conductor 23S1 was measured as approximately 50 ohms with a divider element fully covered with a conductive layer, which is the desired value; and, accordingly, no changes have to be made for this conductor position.

[0086] The following table lists representative values for each cell. Percent of Width of Opening Conductor Initial Impedance for Vertical Pattern Remaining for Conductor (Ohms) (mils) Horizontal Pattern 23S1 50  0  100% 23S3 38.2 101 49.5% 23S4 37.0 104   48%

[0087] In the cases of signal conductors 23S2, 23S3, and 23S4, it is seen that because the initial characteristic impedance varies only slightly from cell to cell; and, consequently, the required patterns vary only slightly from cell to cell. FIG. 11 shows the completed vertical pattern divider element 60. No opening is present in the conductive layer 36 at the location corresponding to signal conductor 23S1. Openings 61-63 are formed at widths of 0.098 in., 0.101 in., and 0.104 in. to correspond to signal conductors 23S2, 23S3, and 23S4 respectively in accordance with the test results.

[0088]FIG. 12 shows the completed horizontal pattern divider element 70. Note that in FIG. 12, there are ten horizontal openings 71 in the conductive layer 36 spanning the positions corresponding to signal conductors 23S2 through 23S4 with slightly stepped sides, following the near linear results indicated in the above table. Given the near linear relationships, it may be possible to perform measurements at just two similar cells and to then extrapolate the results to additional cells along a row.

[0089] The foregoing explanation has considered simple vertical and horizontal patterns. More complex patterns may also be used if desired. Once the style of a pattern has been decided upon, test dividers having a range of variations of the patterns is designed. These are then used experimentally to evaluate the patterns and to determine parameters for the patterns for the actual dividers to meet the given requirements. Also, in cases where it is desirable that the divider also provide a degree of shielding as in non-checkerboard conductor arrangements, the test dividers may additionally be used to evaluate the shielding properties of the patterns under consideration by making appropriate cross talk measurements.

Adjusting Conductor Sizes and/or Spacing

[0090] The characteristic impedance of a particular conductor in a row of conductors can alternatively be adjusted or tuned by varying the size of the conductor, the spacing between conductors, or both. FIG. 13a shows a sectional view of a row of conductors 23 s 1,23 g 1,23 s 2,23 g 2,23 s 3,23 g 3,23 s 4,23 g 4 in which the diameter of signal conductors 23 s 2,23 s 3,23 s 4 are decreased to increase their characteristic impedance. FIG. 13b shows a sectional view of a row of conductors 23 s 1,23 g 1,23 s 2,23 g 2,23 s 3,23 g 3,23 s 4,23 g 4 in which the diameter of ground conductors 23 g 1,23 g 2,23 g 3,23 g 4 are decreased to increase the characteristic impedance in the adjacent signal conductors. FIG. 14 shows a sectional view of a row of conductors 23 s 1,23 g 1,23 s 2,23 g 2,23 s 3,23 g 3,23 s 4, 23 g 4 in which the signal conductor-to-ground conductor spacing for signal conductors 23 s 2,23 s 3,23 s 4 is increased to increase their characteristic impedance. 

What is claimed:
 1. An interface apparatus for integrated circuit testing, the apparatus comprising: a first plate having first locations; a second plate having second locations; conductors extending between said first locations on said first plate and said second locations on said second plate; and a conductive divider element spanning across ones of said conductors, and comprising a pattern of conductive material.
 2. An apparatus according to claim 1, wherein said pattern of conductive material includes non-conductive portions situated between conductive portions of said pattern.
 3. An apparatus according to claim 2, wherein said conductive portions comprise a metal layer and said non-conductive portions comprise openings in said metal layer.
 4. An interface apparatus for integrated circuit testing according to claim 1, wherein said pattern is selected to a provide a predetermined characteristic impedance to at least one of said conductors.
 5. An interface apparatus for integrated circuit testing according to claim 4, wherein said characteristic impedance varies depending upon distance between said pattern and said conductors.
 6. An interface apparatus, comprising: a plurality of plates; a plurality of conductors arranged in rows and extending between said plates; and a divider element situated between two rows of conductors, said divider element including a conductive sheeting with a non-conductive area situated therein.
 7. A method of providing an interface apparatus, said method comprising the steps of: providing a plurality of plates; providing a plurality of conductors in rows and extending between said plates; identifying a location between two rows of said conductors at which a divider element is to be situated, and forming a conductive pattern on said divider element and locating it in said location to attempt to provide an expected affect on the characteristic impedance of ones of said conductors.
 8. A method of providing an interface apparatus according to claim 7, said method further comprising the steps of: measuring how said divider element affects characteristic impedance of said ones of said conductors; and modifying said conductive pattern so that an actual affect on characteristic impedance of ones of said conductors is closer to said expected affect.
 9. A method of providing an interface apparatus according to claim 7, wherein said conductive pattern is formed based upon spatial relationships between and dimensions of said ones of said conductors and said conductive pattern.
 10. An interface apparatus, comprising: a plurality of plates; a plurality of conductors arranged in rows and extending between said plates; wherein first ones of said conductors have a first cross-sectional area and second ones of said conductors have a second cross-sectional area to provide a desired characteristic impedance in at least one of said first ones of said conductors and said second ones of said conductors.
 11. An interface apparatus of claim 10, wherein said desired characteristic impedance of said first ones of said conductors and said second ones of said conductors are substantially equal.
 12. An interface apparatus, comprising: a plurality of plates; a plurality of signal conductors and ground conductors alternately arranged in rows and extending between said plates; wherein first ones of said ground conductors have a first cross-sectional area and second ones of said ground conductors have a second cross-sectional area to provide a desired characteristic impedance in at least one of said signal conductors adjacent said first ones of said conductors and said second ones of said conductors.
 13. An interface apparatus of claim 12, wherein said desired characteristic impedance of said signal conductors adjacent said first ones of said conductors and said second ones of said conductors is substantially equal.
 14. An interface apparatus, comprising: a plurality of plates; a plurality of signal conductors and ground conductors arranged in rows and extending between said plates; wherein the spacing between said signal conductors and said ground conductors is varied to provide desired characteristic impedances in said signal conductors.
 15. An interface apparatus according to claim 14, wherein said characteristic impedances in said signal conductors are substantially equal.
 16. A divider element for affecting the characteristic impedance in one or more conductors in an adjacent row of conductors within an interface apparatus for integrated circuit testing, the divider element comprising a pattern of conductive material with non-conductive areas situated therein. 